.SUBCKT ECF10N20 1 2 3 ********************************************** * Model Generated by PEDC * *Copyright(c) Power Electronics Design Centre* * All Rights Reserved * * Power Electronics Design Centre * * Dept of Elec & Electronic Engineering * * University of Wales Swansea * * Singleton Park * * Swansea SA2 8PP * * Tel : +44 (0)1792 295420 * * Fax : +44 (0)1792 295686 * * E-mail : pedc@swansea.ac.uk * ********************************************** * Model generated on Dec 6 1999 * MODEL FORMAT: SPICE Level 1 * External Node Designations * Node 1 -> Drain * Node 2 -> Gate * Node 3 -> Source * * * * O [1] * | * Z * Z Rd * Z * D2 | * Cdg0 | \|| [9] * |-||--| >|O---O-----| * | | /|| | | * [2] Rg | ||---| Z --- * 0--/\/\/\/\-O----|| M1 Z / \D1 * |[7] ||---| Z --- * | | Z | * | Cgs0 | |RDS | * |-----||--O---O-----| * | [8] * | * O * | * Z * Z Rs * Z * | * O [3] M1 9 7 8 8 MM L=1 W=1 * Default values used in MM: * The capacitances are added externally * Other default values are: * RS=0 RD=0 LD=0 CBD=0 CBS=0 CGBO=0 .MODEL MM NMOS LEVEL=1 IS=1e-32 +VTO=0.635 LAMBDA=0.11 KP=2.376 RS 8 3 0.427 D1 8 9 MD .MODEL MD D IS=1.0e-32 N=50 BV=250 +CJO=1.0e-9 VJ=0.7 M=0.5 RDS 8 9 1e+06 RD 9 1 0.62 RG 2 7 80 * Gate Source capacitance Cgs0 CAP1 7 8 480e-12 ************************* * Gate Drain capacitance Cdg0 CAP 7 4 12.2e-12 ************************* * Gate Drain Capacitance Cdgj0 * Modelled as a diode D2 4 9 MDD .MODEL MDD D IS=1e-32 N=50 +CJO=75.4e-12 VJ=0.174 M=1 ************************* .ENDS ECF10N20 .SUBCKT ECF10N25 1 2 3 ********************************************** * Model Generated by PEDC * *Copyright(c) Power Electronics Design Centre* * All Rights Reserved * * Power Electronics Design Centre * * Dept of Elec & Electronic Engineering * * University of Wales Swansea * * Singleton Park * * Swansea SA2 8PP * * Tel : +44 (0)1792 295420 * * Fax : +44 (0)1792 295686 * * E-mail : pedc@swansea.ac.uk * ********************************************** * Model generated on Nov 30 1999 * MODEL FORMAT: SPICE Level 1 * External Node Designations * Node 1 -> Drain * Node 2 -> Gate * Node 3 -> Source * * * * O [1] * | * Z * Z Rd * Z * D2 | * Cdg0 | /|| [9] * |-||--|/ |O---O-----| * | |\ || | | * [2] Rg | ||---| Z --- * 0--/\/\/\/\-O----|| M1 Z / \D1 * |[7] ||---| Z --- * | | Z | * | Cgs0 | |RDS | * |-----||--O---O-----| * | [8] * | * O * | * Z * Z Rs * Z * | * O [3] M1 9 7 8 8 MM L=1 W=1 * Default values used in MM: * The capacitances are added externally * Other default values are: * RS=0 RD=0 LD=0 CBD=0 CBS=0 CGBO=0 .MODEL MM NMOS LEVEL=1 IS=1e-32 +VTO=0.45 LAMBDA=0.1 KP=1.42 RS 8 3 0.39 D1 8 9 MD .MODEL MD D IS=1.0e-32 N=50 BV=250 +CJO=1.0e-9 VJ=0.266 M=0.922 RDS 8 9 1e+06 RD 9 1 0.55 RG 2 7 72.8 * Gate Source capacitance Cgs0 CAP1 7 8 400e-12 ************************* * Gate Drain capacitance Cdg0 CAP 7 4 8.9e-12 ************************* * Gate Drain Capacitance Cdgj0 * Modelled as a diode D2 4 9 MDD .MODEL MDD D IS=1e-32 N=50 +CJO=97.9e-12 VJ=0.261 M=1 ************************* .ENDS ECF10N25 .SUBCKT ECF10P20 1 2 3 ********************************************** * Model Generated by PEDC * *Copyright(c) Power Electronics Design Centre* * All Rights Reserved * * Power Electronics Design Centre * * Dept of Elec & Electronic Engineering * * University of Wales Swansea * * Singleton Park * * Swansea SA2 8PP * * Tel : +44 (0)1792 295420 * * Fax : +44 (0)1792 295686 * * E-mail : pedc@swansea.ac.uk * ********************************************** * Model generated on Dec 6 1999 * MODEL FORMAT: SPICE Level 1 * External Node Designations * Node 1 -> Drain * Node 2 -> Gate * Node 3 -> Source * * * * O [1] * | * Z * Z Rd * Z * D2 | * Cdg0 | /|| [9] * |-||--|< |O---O-----| * | [4]| \|| | | * [2] Rg | ||---| Z --- * 0--/\/\/\/\-O----|| M1 Z \ /D1 * |[7] ||---| Z --- * | | Z | * | Cgs0 | |RDS | * |-----||--O---O-----| * | [8] * | * O * | * Z * Z Rs * Z * | * O [3] M1 9 7 8 8 MM L=1 W=1 * Default values used in MM: * The capacitances are added externally * Other default values are: * RS=0 RD=0 LD=0 CBD=0 CBS=0 CGBO=0 .MODEL MM PMOS LEVEL=1 IS=1e-32 +VTO=-0.537 LAMBDA=0.049 KP=0.611 RS 8 3 0.315 D1 9 8 MD .MODEL MD D IS=1.0e-32 N=50 BV=250 +CJO=1.45e-9 VJ=0.446 M=0.377 RDS 8 9 1e+06 RD 9 1 0.567 RG 2 7 25.2 * Gate Source capacitance Cgs0 CAP1 7 8 696e-12 ************************* * Gate Drain capacitance Cdg0 CAP 7 4 15.2e-12 ************************* * Gate Drain Capacitance Cdgj0 * Modelled as a diode D2 9 4 MDD .MODEL MDD D IS=1e-32 N=50 +CJO=27.6e-12 VJ=0.817 M=0.871 ************************* .ENDS ECF10P20 .SUBCKT ECF10P25 1 2 3 ********************************************** * Model Generated by PEDC * *Copyright(c) Power Electronics Design Centre* * All Rights Reserved * * Power Electronics Design Centre * * Dept of Elec & Electronic Engineering * * University of Wales Swansea * * Singleton Park * * Swansea SA2 8PP * * Tel : +44 (0)1792 295420 * * Fax : +44 (0)1792 295686 * * E-mail : pedc@swansea.ac.uk * ********************************************** * Model generated on Feb 7 2000 * MODEL FORMAT: SPICE Level 1 * External Node Designations * Node 1 -> Drain * Node 2 -> Gate * Node 3 -> Source * * * * O [1] * | * Z * Z Rd * Z * D2 | * Cdg0 | /|| [9] * |-||--|< |O---O-----| * | [4]| \|| | | * [2] Rg | ||---| Z --- * 0--/\/\/\/\-O----|| M1 Z \ /D1 * |[7] ||---| Z --- * | | Z | * | Cgs0 | |RDS | * |-----||--O---O-----| * | [8] * | * O * | * Z * Z Rs * Z * | * O [3] M1 9 7 8 8 MM L=1 W=1 * Default values used in MM: * The capacitances are added externally * Other default values are: * RS=0 RD=0 LD=0 CBD=0 CBS=0 CGBO=0 .MODEL MM PMOS LEVEL=1 IS=1e-32 +VTO=-0.273 LAMBDA=0.5 KP=0.548 RS 8 3 0.577 D1 9 8 MD .MODEL MD D IS=1.0e-32 N=50 BV=250 +CJO=1e-9 VJ=0.7 M=0.5 RDS 8 9 1e+06 RD 9 1 0.465 RG 2 7 7.19 * Gate Source capacitance Cgs0 CAP1 7 8 2.25e-9 ************************* * Gate Drain capacitance Cdg0 CAP 7 4 41e-12 ************************* * Gate Drain Capacitance Cdgj0 * Modelled as double diode D2 9 10 MDD D3 4 10 MDD .MODEL MDD D IS=1e-32 N=50 +CJO=184e-12 VJ=0.7 M=0.5 ************************* .ENDS ECF10P25 .SUBCKT ECF20N20 1 2 3 ********************************************** * Model Generated by PEDC * *Copyright(c) Power Electronics Design Centre* * All Rights Reserved * * Power Electronics Design Centre * * Dept of Elec & Electronic Engineering * * University of Wales Swansea * * Singleton Park * * Swansea SA2 8PP * * Tel : +44 (0)1792 295420 * * Fax : +44 (0)1792 295686 * * E-mail : pedc@swansea.ac.uk * ********************************************** * Model generated on Dec 6 1999 * MODEL FORMAT: SPICE Level 1 * External Node Designations * Node 1 -> Drain * Node 2 -> Gate * Node 3 -> Source * * * * O [1] * | * Z * Z Rd * Z * D2 | * Cdg0 | \|| [9] * |-||--| >|O---O-----| * | | /|| | | * [2] Rg | ||---| Z --- * 0--/\/\/\/\-O----|| M1 Z / \D1 * |[7] ||---| Z --- * | | Z | * | Cgs0 | |RDS | * |-----||--O---O-----| * | [8] * | * O * | * Z * Z Rs * Z * | * O [3] M1 9 7 8 8 MM L=1 W=1 * Default values used in MM: * The capacitances are added externally * Other default values are: * RS=0 RD=0 LD=0 CBD=0 CBS=0 CGBO=0 .MODEL MM NMOS LEVEL=1 IS=1e-32 +VTO=0.362 LAMBDA=0.06 KP=3.097 RS 8 3 0.178 D1 8 9 MD .MODEL MD D IS=1.0e-32 N=50 BV=250 +CJO=1.77e-9 VJ=0.1 M=0.28 RDS 8 9 1e+06 RD 9 1 0.265 RG 2 7 42 * Gate Source capacitance Cgs0 CAP1 7 8 900e-12 ************************* * Gate Drain capacitance Cdg0 CAP 7 4 18.7e-12 ************************* * Gate Drain Capacitance Cdgj0 * Modelled as a diode D2 4 9 MDD .MODEL MDD D IS=1e-32 N=50 +CJO=75e-12 VJ=0.1 M=0.768 ************************* .ENDS ECF20N20 .SUBCKT ECF20N25 1 2 3 ********************************************** * Model Generated by PEDC * *Copyright(c) Power Electronics Design Centre* * All Rights Reserved * * Power Electronics Design Centre * * Dept of Elec & Electronic Engineering * * University of Wales Swansea * * Singleton Park * * Swansea SA2 8PP * * Tel : +44 (0)1792 295420 * * Fax : +44 (0)1792 295686 * * E-mail : pedc@swansea.ac.uk * ********************************************** * Model generated on Dec 9 1999 * MODEL FORMAT: SPICE Level 1 * External Node Designations * Node 1 -> Drain * Node 2 -> Gate * Node 3 -> Source * * * * O [1] * | * Z * Z Rd * Z * D2 | * Cdg0 |\ || [9] * |-||--| >|O---O-----|--------| * | [4]|/ || | | | * [2] Rg | ||---| Z --- __|__ * 0--/\/\/\/\-O----|| M1 Z / \D1 _____ * |[7] ||---| Z --- |Cds0 * | | Z | | * | Cgs0 | |RDS | | * |-----||--O---O-----|--------| * | [8] * | * O * | * Z * Z Rs * Z * | * O [3] M1 9 7 8 8 MM L=1 W=1 * Default values used in MM: * With the exception of Cgs0 the capacitances are * added externally * Other default values are: * RS=0 RD=0 LD=0 CBD=0 CBS=0 CGBO=0 .MODEL MM NMOS LEVEL=1 IS=1e-32 CGSO=1.57e-9 +VTO=0.414 LAMBDA=0.104 KP=2.808 RS 8 3 0.191 D1 8 9 MD .MODEL MD D IS=1.0e-32 N=50 BV=250 +CJO=1.54e-9 VJ=0.633 M=0.479 RDS 8 9 1e+06 RD 9 1 0.289 RG 2 7 13.3 * Drain Source capacitance Cds0 CAP1 9 8 403e-12 ************************* * Gate Drain capacitance Cdg0 CAP 7 4 25.6e-12 ************************* * Gate Drain Capacitance Cdgj0 * Modelled as a diode D2 4 9 MDD .MODEL MDD D IS=1e-32 N=50 +CJO=137e-12 VJ=0.7 M=0.5 ************************* .ENDS ECF20N25 .SUBCKT ECF20P20 1 2 3 ********************************************** * Model Generated by PEDC * *Copyright(c) Power Electronics Design Centre* * All Rights Reserved * * Power Electronics Design Centre * * Dept of Elec & Electronic Engineering * * University of Wales Swansea * * Singleton Park * * Swansea SA2 8PP * * Tel : +44 (0)1792 295420 * * Fax : +44 (0)1792 295686 * * E-mail : pedc@swansea.ac.uk * ********************************************** * Model generated on Feb 7 2000 * MODEL FORMAT: SPICE Level 1 * External Node Designations * Node 1 -> Drain * Node 2 -> Gate * Node 3 -> Source * * * * O [1] * | * Z * Z Rd * Z * D2 | * Cdg0 | /|| [9] * |-||--|< |O---O-----| * | [4]| \|| | | * [2] Rg | ||---| Z --- * 0--/\/\/\/\-O----|| M1 Z \ /D1 * |[7] ||---| Z --- * | | Z | * | Cgs0 | |RDS | * |-----||--O---O-----| * | [8] * | * O * | * Z * Z Rs * Z * | * O [3] M1 9 7 8 8 MM L=1 W=1 * Default values used in MM: * The capacitances are added externally * Other default values are: * RS=0 RD=0 LD=0 CBD=0 CBS=0 CGBO=0 .MODEL MM PMOS LEVEL=1 IS=1e-32 +VTO=-0.273 LAMBDA=0.5 KP=0.548 RS 8 3 0.171 D1 9 8 MD .MODEL MD D IS=1.0e-32 N=50 BV=250 +CJO=1e-9 VJ=0.7 M=0.5 RDS 8 9 1e+06 RD 9 1 0.259 RG 2 7 45 * Gate Source capacitance Cgs0 CAP1 7 8 1.08e-9 ************************* * Gate Drain capacitance Cdg0 CAP 7 4 36e-12 ************************* * Gate Drain Capacitance Cdgj0 * Modelled as double diode D2 9 10 MDD D3 4 10 MDD .MODEL MDD D IS=1e-32 N=50 +CJO=762e-12 VJ=0.1 M=1 ************************* .ENDS ECF20P20 .SUBCKT ECF20P25 1 2 3 ********************************************** * Model Generated by PEDC * *Copyright(c) Power Electronics Design Centre* * All Rights Reserved * * Power Electronics Design Centre * * Dept of Elec & Electronic Engineering * * University of Wales Swansea * * Singleton Park * * Swansea SA2 8PP * * Tel : +44 (0)1792 295420 * * Fax : +44 (0)1792 295686 * * E-mail : pedc@swansea.ac.uk * ********************************************** * Model generated on Feb 7 2000 * MODEL FORMAT: SPICE Level 1 * External Node Designations * Node 1 -> Drain * Node 2 -> Gate * Node 3 -> Source * * * * O [1] * | * Z * Z Rd * Z * D2 | * Cdg0 | /|| [9] * |-||--|< |O---O-----| * | [4]| \|| | | * [2] Rg | ||---| Z --- * 0--/\/\/\/\-O----|| M1 Z \ /D1 * |[7] ||---| Z --- * | | Z | * | Cgs0 | |RDS | * |-----||--O---O-----| * | [8] * | * O * | * Z * Z Rs * Z * | * O [3] M1 9 7 8 8 MM L=1 W=1 * Default values used in MM: * The capacitances are added externally * Other default values are: * RS=0 RD=0 LD=0 CBD=0 CBS=0 CGBO=0 .MODEL MM PMOS LEVEL=1 IS=1e-32 +VTO=-0.697 LAMBDA=0.5 KP=1.87 RS 8 3 0.283 D1 9 8 MD .MODEL MD D IS=1.0e-32 N=50 BV=250 +CJO=2.1e-12 VJ=0.7 M=0.5 RDS 8 9 1e+06 RD 9 1 0.224 RG 2 7 77.9 * Gate Source capacitance Cgs0 CAP1 7 8 600e-12 ************************* * Gate Drain capacitance Cdg0 CAP 7 4 4.83e-12 ************************* * Gate Drain Capacitance Cdgj * Modelled as double diode D2 9 10 MD0 D3 4 10 MD1 .MODEL MD0 D IS=1e-32 N=50 +CJO=39.8e-12 VJ=0.7 M=0.5 .MODEL MD1 D IS=1e-32 N=50 +CJO=1.67e-9 VJ=0.7 M=0.5 ************************* .ENDS ECF20P25 .SUBCKT ECX10N20 1 2 3 ********************************************** * Model Generated by PEDC * *Copyright(c) Power Electronics Design Centre* * All Rights Reserved * * Power Electronics Design Centre * * Dept of Elec & Electronic Engineering * * University of Wales Swansea * * Singleton Park * * Swansea SA2 8PP * * Tel : +44 (0)1792 295420 * * Fax : +44 (0)1792 295686 * * E-mail : pedc@swansea.ac.uk * ********************************************** * Model generated on Dec 6 1999 * MODEL FORMAT: SPICE Level 1 * External Node Designations * Node 1 -> Drain * Node 2 -> Gate * Node 3 -> Source * * * * O [1] * | * Z * Z Rd * Z * D2 | * Cdg0 | \|| [9] * |-||--| >|O---O-----| * | | /|| | | * [2] Rg | ||---| Z --- * 0--/\/\/\/\-O----|| M1 Z / \D1 * |[7] ||---| Z --- * | | Z | * | Cgs0 | |RDS | * |-----||--O---O-----| * | [8] * | * O * | * Z * Z Rs * Z * | * O [3] M1 9 7 8 8 MM L=1 W=1 * Default values used in MM: * The capacitances are added externally * Other default values are: * RS=0 RD=0 LD=0 CBD=0 CBS=0 CGBO=0 .MODEL MM NMOS LEVEL=1 IS=1e-32 +VTO=0.473 LAMBDA=0.092 KP=1.585 RS 8 3 0.41 D1 8 9 MD .MODEL MD D IS=1.0e-32 N=50 BV=250 +CJO=1.0e-9 VJ=0.7 M=0.5 RDS 8 9 1e+06 RD 9 1 0.58 RG 2 7 80 * Gate Source capacitance Cgs0 CAP1 7 8 400e-12 ************************* * Gate Drain capacitance Cdg0 CAP 7 4 10.5e-12 ************************* * Gate Drain Capacitance Cdgj0 * Modelled as a diode D2 4 9 MDD .MODEL MDD D IS=1e-32 N=50 +CJO=94.8e-12 VJ=0.3 M=1 ************************* .ENDS ECX10N20 .SUBCKT ECX10P20 1 2 3 ********************************************** * Model Generated by PEDC * *Copyright(c) Power Electronics Design Centre* * All Rights Reserved * * Power Electronics Design Centre * * Dept of Elec & Electronic Engineering * * University of Wales Swansea * * Singleton Park * * Swansea SA2 8PP * * Tel : +44 (0)1792 295420 * * Fax : +44 (0)1792 295686 * * E-mail : pedc@swansea.ac.uk * ********************************************** * Model generated on Dec 6 1999 * MODEL FORMAT: SPICE Level 1 * External Node Designations * Node 1 -> Drain * Node 2 -> Gate * Node 3 -> Source * * * * O [1] * | * Z * Z Rd * Z * D2 | * Cdg0 | /|| [9] * |-||--|< |O---O-----| * | [4]| \|| | | * [2] Rg | ||---| Z --- * 0--/\/\/\/\-O----|| M1 Z \ /D1 * |[7] ||---| Z --- * | | Z | * | Cgs0 | |RDS | * |-----||--O---O-----| * | [8] * | * O * | * Z * Z Rs * Z * | * O [3] M1 9 7 8 8 MM L=1 W=1 * Default values used in MM: * The capacitances are added externally * Other default values are: * RS=0 RD=0 LD=0 CBD=0 CBS=0 CGBO=0 .MODEL MM PMOS LEVEL=1 IS=1e-32 +VTO=-0.426 LAMBDA=0.073 KP=0.673 RS 8 3 0.342 D1 9 8 MD .MODEL MD D IS=1.0e-32 N=50 BV=250 +CJO=1.45e-9 VJ=0.446 M=0.377 RDS 8 9 1e+06 RD 9 1 0.523 RG 2 7 45.2 * Gate Source capacitance Cgs0 CAP1 7 8 696e-12 ************************* * Gate Drain capacitance Cdg0 CAP 7 4 15.2e-12 ************************* * Gate Drain Capacitance Cdgj0 * Modelled as a diode D2 9 4 MDD .MODEL MDD D IS=1e-32 N=50 +CJO=27.6e-12 VJ=0.817 M=0.871 ************************* .ENDS ECX10P20